ESMT
M12S64322A
Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
*Note1
tRC
tRCD
RAS
*Note2
CAS
ADDR
Rb
Cb
Ra
Ca
BA1
BA0
Rb
`
A10/AP
CL=2
Ra
tOH
Qa2
Qa3
Db2
Qa0
Db1
Db3
Qa1
Db0
Db0
tSAC
tSHZ
*Note3
tSHZ
tRDL
tRDL
DQ
tOH
CL=3
Qa1
Qa2
Db1
Qa0
Qa3
Db2
Db3
tSAC
*Note3
WE
DQM
Precharge
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Read
Write
(A-Bank)
(A-Bank)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 32/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
