ESMT
M12S64322A
Page Read Cycle at Different Bank @ Burst Length = 4
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C L O C K
C K E
H I G H
* N o t e 1
C S
R A S
* N o t e 2
C A S
A D D R
BA1
R A a
R C c
R B b C A a
C B b
R D d C C c
C D d
BA0
A10/AP
CL= 2
R A a
R B b
R C c
R D d
QAa0
QDd0
QCc2
QCc1
QAa1
QAa0
QDd2
QDd1
QAa2
QBb1 QBb2
QBb0
QC c0
QBb2
D Q
CL= 3
QBb1
QDd1
QDd2
QAa1 QAa2 QBb0
QC c2 QD d0
QCc0 QC c1
W E
D Q M
P r e c h a r g e
( D - B a n k )
R e a d
( B - B a n k )
R e a d
( A - B a n k )
R e a d
( C - B a n k )
R e a d
( D - B a n k )
R o w A c t i v e
( A - B a n k )
R o w A c t i v e
( D - B a n k )
P r e c h a r g e
( C - B a n k )
R o w A c t i v e
( B - B a n k )
R o w A c t i v e
( C - B a n k )
P r e c h a r g e
( A - B a n k )
P r e c h a r g e
( B - B a n k )
: D o n ' t C a r e
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 34/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
