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M12S16161A-10TG 参数 Datasheet PDF下载

M12S16161A-10TG图片预览
型号: M12S16161A-10TG
PDF下载: 下载PDF文件 查看货源
内容描述: 512K X 16位X 2Banks同步DRAM [512K x 16Bit x 2Banks Synchronous DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 28 页 / 866 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
DQ0 ~ 15
VDD/VSS
VDDQ/VSSQ
N.C/RFU
Data Input / Output
Power Supply/Ground
Data Output Power/Ground
No Connection/
Reserved for Future Use
M12S16161A
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
,V
OUT
V
DD
,V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ + 150
0.7
50
Unit
V
V
°
C
W
MA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0
°C
~ 70
°C
)
Parameter
Supply voltage
Symbol
V
DD
V
DDQ
Min
2.3
2.3
Typ
2.5
2.5
Max
2.7
2.7
Unit
V
V
Note
1.65
-
2.7
V
1
Input logic high voltage
V
IH
0.8 x V
DDQ
-
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.3
V
2
Output logic high voltage
V
OH
V
DDQ
– 0.2
-
-
V
I
OH
=-0.1mA
Output logic low voltage
V
OL
-
-
0.2
V
I
OL
= 0.1mA
Input leakage current
I
IL
-10
-
10
uA
3
Output leakage current
I
OL
-10
-
10
uA
4
Note :
1. ESMT can support VDDQ 2.5V (in general case) and 1.8V (in specific case) for VDD 2.5V products. Please contact
to sales. Dept. when condisering the use fo VDDQ 1.8V (min 1.65V).
2.V
IH
(max) = 4.6V AC for pulse width
3ns acceptable.
3.V
IL
(min) = -1.0V AC for pulse width
3ns acceptable.
4.Any input 0V
V
IN
V
DDQ
, all other pins are not under test = 0V.
5.Dout is disabled, 0V
V
OUT
V
DDQ
.
CAPACITANCE
(V
DD
= 2.5V, T
A
= 25
°C
, f = 1MHz)
Pin
CLOCK
RAS , CAS ,
WE
, CS , CKE, LDQM,
UDQM
ADDRESS
DQ0 ~DQ15
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
-
-
-
-
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2005
Revision
:
1.0
3/28