ESMT
M12L64164A
Operation Temperature Condition -40°C~85°C
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
H I G H
C K E
C S
t R C D
R A S
C A S
* N o t e 2
A D D R
R a
C a
C d
C b
C c
A13
A12
A10/AP
R a
tR D L
Qa0
Dc 1
CL = 2
Qa1
Qa0
Qb0 Qb1
Dc 0
Dc 0
Dd1
Qb2
Qb1
Dd0
D Q
Qb0
Qa1
CL = 3
Dc 1 Dd0
Dd1
tC D L
W E
* N o t e 1
* N o t e 3
D Q M
Read
( A - Bank )
Read
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Write
( A - Bank )
Precharge
( A
- B an k )
: D o n ' t C a r e
Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid
bus contention.
2. Row precharge will interrupt writing. Last data input , tRDL before row precharge , will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2007
Revision: 1.2 32/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
