ESMT
M12L64164A
Operation Temperature Condition -40°C~85°C
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
H I G H
C K E
C S
R A S
C A S
A D D R
CA b
CA a
RA a
A13
A12
A10/AP
RA a
1
1
CL= 2
D Q
QAa0
QAa1 QAa2
QAb1 QAb5
QAb2 QAb3 QAb4
QAa3 QAa4
QAb0
2
2
CL= 3
QAa2
QAa4
QAb5
QAa1
QAa3
QAb0 QAb1
QAb4
QAb2 QAb3
QAa0
* N o t e 1
W E
D Q M
Read
(A - Ban k )
Burst Stop
Read
(A - Ban k )
Prechar ge
( A- B an k )
Row A c t i ve
( A- B an k )
:D on' t C ar e
*Note : 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2007
Revision: 1.2 38/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
