ESMT
M12L64164A
Operation Temperature Condition -40°C~85°C
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
15
16
17
19
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
C B c
C D b
R D b
R B c
RA a
CA a
A13
A12
A10/AP
CL = 2
RB b
R A c
Ddb1
Ddb1
RA a
* N o t e 1
tC D L
DD d3
QBc0
DD b0
DD b0
DD b2
QAa3
QBc1 QBc2
QAa0 QAa1 QAa2
D Q
CL = 3
QAa3
QAa0
DD b2 DD d3
QAa1 QAa2
QBc0
QBc1
W E
D Q M
Read
(B - Ban k )
W r i t e
( D - B an k )
Read
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: D o n ' t C a r e
*Note : 1. tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2007
Revision: 1.2 35/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
