ESMT
M12L64164A (2Y)
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
16
17
18
11
12
13
14
15
19
0
1
2
5
9
1 0
3
4
6
7
8
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
R A a
C A b
C A a
B A 0
B A 1
R A a
A 10/AP
t
R D L
t
B D L
* N o t e 1
D Ab 0
D Ab 1 DA b 2 DA b 3 D Ab 4
DA b 5
D Q
W E
DA a 3 D Aa 4
DA a 2
D Aa 0 D Aa 1
D Q M
W r i t e
( A - B a n k )
B u rs t S t o p
R o w A c t i ve
( A - B a n k)
P r e c h a rg e
( A - B a n k)
W r i t e
( A - B a n k )
: D o n ' t C a r e
*Note: 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2012
Revision: 1.1 38/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
