ESMT
M12L64164A (2Y)
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
C S
R A S
C A S
A D D R
C a
R a
C c
C b
BA0
BA1
A 10/A P
D Q
R a
Q a 0
Q a 2
Q a 1
Q a 3
Q b 0 Q b 1
D c 0
D c 2
t
S H Z
t
S H Z
W E
* N o t e 1
D Q M
C l oc k
S u pe n s i o n
W r i t e
D Q M
R o w A c t i v e
R e a d
R e a d
W r i t e
D Q M
R e a d D Q M
W r i t e
C l o ck
S us p e ns io n
: D o n ' t C a r e
*Note: 1. DQM is needed to prevent bus contention
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2012
Revision: 1.1 36/45