ESMT
M12L64164A (2Y)
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
1 0
11
12
13
14
18
15
16
17
19
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
C B c
C D b
R D b
R B c
R A a
C A a
BA0
BA1
A 1 0/A P
R B b
R A c
R A a
* N o t e 1
t
C D L
C L = 2
D Q
Q B c 0
D D b 0
D D b 0
QA a 3
QA a 2
D d b 1 D D b 2
D D d 3
Q Bc 1 Q B c 2
Q Aa2
Q Aa1
Q A a0 QAa 1
C L = 3
Q A a3
D d b1
Q A a0
D D b 2 D D d 3
Q B c 0
Q B c 1
W E
D Q M
R e a d
( B - B a n k )
W r i t e
( D - B a n k )
Read
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: D o n ' t C a r e
*Note: 1. tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2012
Revision: 1.1 34/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
