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M12L32162A_0712 参数 Datasheet PDF下载

M12L32162A_0712图片预览
型号: M12L32162A_0712
PDF下载: 下载PDF文件 查看货源
内容描述: 1米x 16Bit的X 2Banks同步DRAM [1M x 16Bit x 2Banks Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 28 页 / 688 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M12L32162A  
Operation Temperature Condition -40°C~105°C  
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)  
-7  
Parameter  
CAS Latency =3  
Symbol  
Unit  
Note  
Min  
7
Max  
CLK cycle time  
tCC  
1000  
CAS Latency =2  
CAS Latency =1  
CAS Latency =3  
CAS Latency =2  
CAS Latency =1  
10  
17  
-
ns  
1
6
6
CLK to valid  
output delay  
tSAC  
ns  
1
-
-
13  
Output data hold time  
CLK high pulse width  
CLK low pulse width  
Input setup time  
tOH  
tCH  
tCL  
ns  
ns  
ns  
ns  
ns  
ns  
2
3
3
3
3
2
2.5  
2.5  
2.5  
2
tSS  
tSH  
tSLZ  
Input hold time  
2
CLK to output in Low-Z  
0
CAS Latency =3  
-
6
6
6
CLK to output in  
Hi-Z  
tSHZ  
CAS Latency =2  
CAS Latency =1  
-
ns  
-
*All AC parameters are measured from half to half.  
Note: 1.Parameters depend on programmed CAS latency.  
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.  
3.Assumed input rise and fall time (tr & tf)=1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the  
parameter.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Dec. 2007  
Revision : 1.2 7/28  
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