ESMT
M12L2561616A (2S)
Operation Temperature Condition -40°C~85°C
Page Write Cycle at Different Bank @ Burst Length = 4
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
11
12
10
C L O C K
C K E
H I G H
C S
R A S
* N o t e 2
C A S
A D D R
R C c
R A a
R B b C A a
C C c
C D d
C B b
R D d
B A 0
B A 1
R B b
R A a
R C c
R D d
A1 0/AP
D Q
DA a 0
D C c 1
D D d 1
DA a 1 D A a 2 D Aa 3 DB b 0 DB b 1
D Bb 3 D C c 0
D D d 0
C D d 2
D Bb 2
t
R D L
t
C D L
W E
* N o t e 1
D Q M
W r i t e
( D - B a n k )
R o w A c t i v e
( D - B a n k )
W r i t e
( B - B a n k )
W r i t e
( A - B a n k )
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
( A - Bank )
R o w A c t i v e
( B - B a n k )
W r i t e
( C - B a n k )
R o w A c t i v e
( C - B a n k )
:
D o n ' t c a r e
*Note: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2015
Revision: 1.4 33/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
