ESMT
M12L2561616A (2S)
Operation Temperature Condition -40°C~85°C
Read & Write Cycle at Same Bank @ Burst Length = 4
13
14
15
16
17
18
19
20
0
1
2
3
4
5
6
7
8
9
11
12
10
C L O C K
H I G H
C K E
* N o t e 1
tR C
C S
tR C D
R A S
C A S
* N o t e 2
C b
Ca
R b
R a
A D D R
B A 0
B A1
A1 0/AP
C L = 2
R a
R b
Q a 0 Q a 1
D b 0 D b 1 D b 2 D b 3
Q a 3
Q a 2
Q a 2
* N o t e 3
D Q
tR D L
C L = 3
Q a 0 Qa 1
D b 1 D b 2
Q a 3
D b 0
D b 3
* N o t e 3
tR D L
W E
D Q M
Precharge
( A - Bank )
Read
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Row Active
A - Bank )
P r e c h a r g e
( A B a n k )
(
-
: D o n ' t C a r e
*Note:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2015
Revision: 1.4 30/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
