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M12L128324A-7TIG 参数 Datasheet PDF下载

M12L128324A-7TIG图片预览
型号: M12L128324A-7TIG
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×32位×4银行同步DRAM [1M x 32 Bit x 4 Banks Synchronous DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器
文件页数/大小: 49 页 / 793 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
°C , f = 1MHZ)
Parameter
Input capacitance (A0 ~ A10, BA0 ~ BA1)
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
& DQM)
Data input/output capacitance (DQ0 ~ DQ31)
Symbol
CIN1
CIN2
COUT
Min
2
2
2
M12L128324A
Operation temperature condition -40
°
C~85
°
C
Max
4
4
5
Unit
pF
pF
pF
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted,T
A
= -40 to 85 °C
CAS
Latency
Version
-6
160
3
1
30
mA
9
7
6
40
15
mA
mA
mA
-7
140
Unit
Note
Parameter
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Symbol
Test Condition
Burst Length = 1
I
CC1
I
CC2P
I
CC2PS
I
CC2N
I
CC2NS
t
RC
t
RC(min)
I
OL
= 0 mA
CKE
V
IL
(max), tcc = 10ns
CKE & CLK
V
IL
(max), t
cc
=
CKE
V
IH
(min), CS
V
IH
(min), t
cc
= 10ns
Input signals are changed one time during 20ns
CKE
V
IH
(min), CLK
V
IL
(max), t
cc
=
input signals are stable
CKE
V
IL
(max), tcc = 10ns
CKE & CLK
V
IL
(max), t
cc
=
CKE
VIH(min), CS
V
IH
(min), tcc = 15ns
Input signals are changed one time during 30ns
CKE
V
IH
(min), CLK
V
IL
(max), tcc =
input signals are stable
IOL = 0 mA
Page Burst
2 Banks activated
t
CK
= t
CK(min)
t
RC
t
RC(min)
CKE
0.2V
mA
1,2
mA
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Note :
I
CC4
270
240
mA
mA
mA
1,2
I
CC5
I
CC6
270
2
240
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1
6/49