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M12L16161A-7TIG2Q 参数 Datasheet PDF下载

M12L16161A-7TIG2Q图片预览
型号: M12L16161A-7TIG2Q
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 28 页 / 706 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
Mode Register
BA
0
BA
X
BA
BA
X
BA
0
A10
0
A10
x
A10
A10
x
A10
0
A9
0
A9
1
A9
A9
x
A9
0
A8
0
A8
0
A8
1
A8
1
A8
0
A7
1
A7
0
A7
0
A7
1
A7
0
A6
A5
A4
A3
A2
A2
A2
A2
v
A2
A1
A1
BL
A1
A1
v
A1
BL
A0
M12L16161A (2Q)
Operation Temperature Condition -40
°
C~85
°
C
JEDEC Standard Test Set (refresh counter test)
A6 A5 A4 A3
LTMODE
WT
A6
A5
A4
A3
A3
v
A3
WT
A0
Burst Read and Single Write (for Write
Through Cache)
A0
Use in future
A6 A5 A4
v
v
v
A6 A5 A4
LTMODE
A0
v
A0
Vender Specific
Mode Register Set
Bit2-0
000
001
010
011
100
101
110
111
v =Valid
x =Don’t care
WT=0
1
2
4
8
R
R
R
Full page
WT=1
1
2
4
8
R
R
R
R
Burst length
Wrap type
0
1
Sequential
Interleave
Latency mode
Bits6-4
000
001
010
011
100
101
110
111
CAS Latency
R
R
2
3
R
R
R
R
Remark R: Reserved
Mode Register Write Timing
CLOCK
CKE
CS
RAS
CAS
WE
A0-A10, BA
Mode Register Write
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Feb. 2012
Revision
:
1.0
7/28