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M12L16161A-7TIG2Q 参数 Datasheet PDF下载

M12L16161A-7TIG2Q图片预览
型号: M12L16161A-7TIG2Q
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 28 页 / 706 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-5
Min
Max
Min
-7
M12L16161A (2Q)
Operation Temperature Condition -40
°
C~85
°
C
Max
Unit
Note
CLK cycle time
CLK to valid
output delay
CAS Latency =3
CAS Latency =2
CAS Latency =3
CAS Latency =2
t
CC
t
SAC
t
OH
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
5
7
-
-
2
2
2
2
1
1
-
-
1000
4.5
5
7
8.6
-
-
2
2
2
2
1
1
1000
6
6
ns
ns
ns
ns
ns
ns
ns
ns
1
1
2
3
3
3
3
2
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output in CAS Latency =3
Hi-Z
CAS Latency =2
4.5
5
-
-
6
6
ns
*All AC parameters are measured from half to half.
Note:
1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Feb. 2012
Revision
:
1.0
6/28