ESMT
Page Read Cycle at Different Bank @ Burst Length = 4
M12L128168A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H I G H
* N o t e 1
C S
R A S
* N o t e 2
C A S
A D D R
A13
C B b
R A a
C A a
R C c
C C c
C D d
R D d
R B b
A12
A10/AP
CL= 2
R C c
R A a
R B b
R D d
QAa0
QAa1
QDd0
QCc2
QAa2 QBb0
QBb1 QBb2
QBb0 QBb1
QCc1 QCc2
QDd1 QDd2
QDd0 QDd1
QCc0
QBb2
D Q
CL= 3
QCc1
QCc0
QDd2
QAa0 QAa1
QAa2
W E
D Q M
P r e c h a r g e
( D - B a n k )
R e a d
( B - B a n k )
R e a d
( A - B a n k )
R e a d
( C - B a n k )
R e a d
( D - B a n k )
R o w A c t i v e
( A - B a n k )
R o w A c t i v e
( D - B a n k )
P r e c h a r g e
( C - B a n k )
R o w A c t i v e
( B - B a n k )
R o w A c t i v e
( C - B a n k )
P r e c h a r g e
( A - B a n k )
P r e c h a r g e
( B - B a n k )
: D o n ' t C a r e
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0 32/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
