ESMT
M12L128168A
Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
C S
R A S
C A S
A D D R
R a
C a
C c
C b
A13
A12
A10/AP
R a
Qa1
Qa2
Dc 0
Qa3
D Q
Qb0
Qb1
Dc 2
Qa0
tS H Z
tS H Z
W E
* N o t e 1
D Q M
Cl oc k
Suspension
W r i t e
D Q M
Row A c t i ve
Read
Rea d
W r i t e
D Q M
Re ad D Q M
W r i t e
Cl oc k
Suspension
:D on' t C ar e
*Note : 1. DQM is needed to prevent bus contention
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0 36/43