$ %
DRAM
FEATURES
y
y
y
y
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
1M x 16 DRAM
EDO PAGE MODE
ORDERING INFORMATION - PACKAGE
42-pin 400mil SOJ
44 / 50-pin 400mil TSOP (TypeII)
PRODUCT NO.
M11B16161A-45J/50J/60J
M11B16161SA-45J/50J/60J
M11L16161A-45J/50J/60J
M11L16161SA-45J/50J/60J
M11B16161A-45T/50T/60T
M11B16161SA-45T/50T/60T
M11L16161A-45T/50T/60T
Refresh Vcc
Normal
*Self-
Refresh
Normal
Self-
Refresh
Normal
*Self-
Refresh
Normal
3.3V
5V
TSOPII
3.3V
5V
SOJ
PACKING
TYPE
y
y
y
y
y
y
X16 organization
EDO (Extended Data-Out) access mode
2
CAS
Byte/Word Read/Write operation
Single power supply :
5V
±
10% Vcc for 5V product
3.3V
±
10% Vcc for 3.3V product
Interface for inputs and outputs
TTL-compatible for 5V products
LVTTL-compatible for 3.3V products
1024-cycle refresh in 16ms
Refresh modes :
RAS
only,
CAS
BEFORE
RAS
(CBR)
and HIDDEN capabilities,
Optional self-Refresh capabilities(S-ver. Only)
JEDEC standard pinout
Key AC Parameter
-45
-50
-60
t
RAC
45
50
60
t
CAC
11
13
15
t
RC
77
84
104
t
PC
16
20
25
M11L16161SA-45T/50T/60T Self-
Refresh
* Ordered by special request
GENERAL DESCRIPTION
The M11B16161/M11L16161 series is a randomly accessed solid state memory, organized as 1,048,576 x 16 bits device. It
offers Extended Data-Output access mode. Single power supply (5V
±
10%, 3.3V
±
10%), access time (-45,-50,-60), self-
refresh function and package type (SOJ, TSOP II) are optional features of this family. All these family have
CAS
- before -
RAS
,
RAS
-only refresh and Hidden refresh.
Two access modes are supported by this device : Byte access and Word access. Use only one of the two
CAS
and leave
the other staying high will result in a BYTE access. WORD access happens when two
CAS
(
CASL
,
CASH
) are used.
CASL
transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and
CASH
transiting low will
output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RA S
NC
NC
A0
A1
A2
A3
V
C C
TSOP (TypeII) Top View
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
CASL
CA S H
OE
A9
A8
A7
A6
A5
A4
V
S S
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
V
CC
I/O 0
I/O 1
I/O 2
I/O 3
V
CC
I/O 4
I/O 5
I/O 6
I/O 7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
I/O1 5
I/O1 4
I/O1 3
I/O1 2
V
SS
I/O1 1
I/O1 0
I/O 9
I/O 8
NC
NC
CA SL
CASH
OE
A9
A8
A7
A6
A5
A4
V
S S
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.3
1/16
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
