$ %
READ CYCLE
t
RC
t
RAS
V
IH
RAS
V
IL
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
t
RP
t
CSH
t
R SH
t
CAS
t
RR H
t
CLCH
t
CR P
CA SL ,CAS H
V
IH
V
IL
t
RCD
t
AR
t
ASR
ADDR
V
IH
V
IL
ROW
t
RAD
t
RAH
t
RAL
t
AS C
t
CAH
COLUMN
t
ACH
ROW
t
RC S
WE
V
IH
V
IL
t
RC H
t
AA
t
RAC
t
CAC
t
CLZ
I/ O
V
OH
V
OL
OP EN
NOTE1
t
OF F1
VAL ID D ATA
OP EN
t
O AC
OE
V
IH
V
IL
t
OFF2
EARLY WRITE CYCLE
t
RC
t
RAS
RA S
V
IH
V
IL
t
RP
t
CRP
CA SL ,CAS H
V
IH
V
IL
t
RCD
t
CSH
t
RSH
t
C AS
t
C L C H
t
AR
t
AS R
ADDR
V
IH
V
IL
ROW
t
RAD
t
RAH
t
AS C
CO LU MN
t
RAL
t
CAH
t
ACH
ROW
t
WCS
t
CWL
t
RWL
t
W CR
t
WCH
t
WP
WE
V
IH
V
IL
t
DS
I/ O
V
IH
V
IL
V
IH
V
IL
t
DH R
t
D H
VAL ID DA TA
OE
DON'T CARE
UNDEFINED
Note: 1. t
OFF1
is referenced from the rising edge of
RAS
or
CAS
, whichever occurs last.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.3
8/16
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
