ESMT
F49L800UA/F49L800BA
7.4 More Device Operations
Hardware Data Protection
Logical Inhibit
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes. In addition, the following hardware
data protection measures prevent accidental erasure or
programming, which might otherwise be caused by
Write cycles are inhibited by holding any one of
=
OE
V ,
IL
= V or
= V . To initiate a write cycle,
WE
CE
IH
IH
and
must be a logical zero while
is a
OE
WE
CE
logical one.
spurious system level signals during V
power-up and
CC
power-down transitions, or from system noise.
Power Supply Decoupling
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
Low VCC Write Inhibit
between its V
and GND.
CC
When V
is less than VLKO, the device does not accept
CC
any write cycles. This protects data during V
power-up
CC
and power-down. The command register and all internal
program/erase circuits are disabled, and the device
Power-Up Sequence
The device powers up in the Read Mode. In addition, the
memory contents may only be altered after successful
completion of the predefined command sequences.
resets. Subsequent writes are ignored until V
is
CC
greater than V
. The system must provide the proper
LKO
signals to the control pins to prevent unintentional writes
when V is greater than V
.
LKO
CC
Power-Up Write Inhibit
Write Pulse "Glitch" Protection
If
=
= V and
= V during power up, the
OE
IH
WE
device does not accept commands on the rising edge of
. The internal state machine is automatically reset to
CE
IL
Noise pulses of less than 5 ns (typical) on
do not initiate a write cycle.
or
WE
CE
WE
reading array data on power-up.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2008
Revision: 1.6 17/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
