ESMT
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/
F49L800UA/F49L800BA
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure the data integrity.
. See
BY
“Write Operation Status” section for more information on
these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. See the Erase/Program Operations
tables in “AC Characteristics” for parameters.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
Sector Erase Command
DQ2, or RY/
. (Refer to “Write Operation Status”
BY
Sector erase is a six-bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command.
section for more information on these status bits.)
Refer to the Erase/Program Operations tables in the
“AC Characteristics” section for parameters.
Sector Erase Suspend/Resume Command
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase
algorithm automatically programs and verifies the
sector for an all zero data pattern prior to electrical
erase. The system is not required to provide any
controls or timings during these operations.
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure (The device “erase suspends” all sectors
selected for erasure.). This command is valid only
during the sector erase operation, including the 50 µs
time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if
written during the chip erase operation or Embedded
Program algorithm. Addresses are “don’t-cares” when
writing the Erase Suspend command as shown in
Table 5.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase
commands may be written. Loading the sector erase
buffer may be done in any sequence, and the number
of sectors may be from one sector to all sectors. The
time between these additional cycles must be less
than 50 μs, otherwise the last address and command
might not be accepted, and erasure may begin.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately
terminates the time-out period and suspends the erase
operation.
It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the
last Sector Erase command is written. If the time
between additional sector erase commands can be
assumed to be less than 50 µs, the system need not
monitor DQ3.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if
a sector is actively erasing or is
erase-suspended. See “Write Operation Status”
section for more information on these status bits.
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the device
to reading array data. The system must rewrite the
command sequence and any additional sector
addresses and commands.
After an erase-suspended program operation is
complete, the system can once again read array data
within non-suspended sectors. The system can
determine the status of the program operation using
the DQ7 or DQ6 status bits, just as in the standard
program operation. See “Write Operation Status” for
more information.
The system can monitor DQ3 to determine if the
sector erase timer has timed out. (See the “DQ3:
Sector Erase Timer” section.) The time-out begins
from the rising edge of the final WE pulse in the
command sequence.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2008
Revision: 1.6
13/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
