ESMT
F25L32PA
Table 5: Device Operation Instruction - Continued
Bus Cycle 1~3
Max.
Freq
Operation
1
2
3
4
5
6
N
SIN SOUT
SIN
SOUT
SIN
SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT
Jedec Read ID
9FH Hi-Z
X
8CH
X
20H
X
16H
-
-
-
-
-
-
-
-
(JEDEC-ID) 9
50MHz
~
00H Hi-Z
01H Hi-Z
X
8CH
X
15H
Read ID (RDID) 11
90H Hi-Z
00H
Hi-Z
00H
Hi-Z
100MHz
X
15H
X
8CH
-
-
Notes:
1. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
3. One bus cycle is eight clock periods.
4. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH
Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH
5. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.
6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
7. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.
8. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
9. The JEDEC-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 16H as
memory capacity.
10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR
can reset WREN.
11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.
12. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in.
13. Dual output data:
IO
IO
0
= (D
6
, D
4
, D
2
, D
0
), (D
6
, D
4
, D
2
, D
0
)
)
1
= (D
7
, D5
, D3
, D1
), (D
7
, D5
, D3
, D1
DOUT0
DOUT1
14. M7-M0: Mode bits. Dual input address:
IO
IO
0
= (A22, A20, A18, A16, A14, A12, A10, A
8
)
(A
6
, A
4
, A
2
, A
0
, M
6
, M
4
, M
2
, M
0
)
1
= (A23, A21, A19, A17, A15, A13, A11, A
9
)
(A7
, A
5
, A
3
, A
1
, M
7
, M
5
, M
3
, M
1
)
Bus Cycle-2
Bus Cycle-3
15. This instruction is recommended when using the Dual Mode bit feature.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0 13/36
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
