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F25L32PA-100PAG 参数 Datasheet PDF下载

F25L32PA-100PAG图片预览
型号: F25L32PA-100PAG
PDF下载: 下载PDF文件 查看货源
内容描述: 3V只有32兆位串行闪存,配有双 [3V Only 32 Mbit Serial Flash Memory with Dual]
分类和应用: 闪存存储
文件页数/大小: 36 页 / 373 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F25L32PA  
INSTRUCTIONS  
Instructions are used to Read, Write (Erase and Program), and  
configure the device. The instruction bus cycles are 8 bits each  
for commands (Op Code), data, and addresses. Prior to  
executing any Page Program, Write Status Register, Sector  
Erase, Block Erase, or Chip Erase instructions, the Write Enable  
(WREN) instruction must be executed first. The complete list of  
the instructions is provided in Table 5. All instructions are  
entered and must be driven high after the last bit of the instruction  
has been shifted in (except for Read, Read ID, Read Status  
Register, Read Electronic Signature instructions). Any low to high  
transition on CE , before receiving the last bit of an instruction  
bus cycle, will terminate the instruction in progress and return the  
device to the standby mode.  
synchronized off a high to low transition of CE . Inputs will be  
accepted on the rising edge of SCK starting with the most  
Instruction commands (Op Code), addresses, and data are all  
input from the most significant bit (MSB) first.  
significant bit. CE must be driven low before an instruction is  
Table 5: Device Operation Instruction  
Bus Cycle 1~3  
4
Max.  
Freq  
Operation  
1
2
3
5
6
N
SIN SOUT  
SIN  
SOUT  
SIN  
SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT  
Read  
Fast Read  
33 MHz 03H Hi-Z A23-A16 Hi-Z  
0BH Hi-Z A23-A16 Hi-Z  
A15-A8 Hi-Z A7-A0 Hi-Z  
A15-A8 Hi-Z A7-A0 Hi-Z  
X
X
DOUT0  
X
X
X
X
DOUT1  
DOUT0  
X
X
cont.  
cont.  
cont.  
Fast Read Dual Output12,13  
Fast Read Dual I/O12, 14  
Sector Erase4 (4K Byte)  
Block Erase4, (64K Byte)  
3BH  
BBH  
A23-A16  
A23-A8  
A15-A8  
A7-A0  
DOUT0~1  
A7-A0, M7-M0  
DOUT0~1  
cont.  
-
-
20H Hi-Z A23-A16 Hi-Z  
D8H Hi-Z A23-A16 Hi-Z  
60H /  
A15-A8 Hi-Z A7-A0 Hi-Z  
A15-A8 Hi-Z A7-A0 Hi-Z  
-
-
-
-
-
-
-
-
-
-
-
-
Chip Erase  
Hi-Z  
-
-
-
-
-
-
-
-
-
-
-
-
C7H  
Up to  
Page Program (PP)  
02H Hi-Z A23-A16 Hi-Z  
A15-A8 Hi-Z A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z 256 Hi-Z  
bytes  
50MHz  
Mode Bit Reset 15  
Deep Power Down (DP)  
Read Status Register  
(RDSR) 6  
FFH Hi-Z FFH  
Hi-Z  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B9h Hi-Z  
-
DOUT  
(S7-S0)  
05H Hi-Z  
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Enable Write Status  
Register (EWSR) 7  
Write Status Register  
(WRSR) 7  
50H Hi-Z  
-
-
DIN  
(S7-S0)  
-
DIN  
(S15-S8)  
-
01H Hi-Z  
06H Hi-Z  
04H Hi-Z  
Hi-Z  
Hi-Z  
-.  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Write Enable (WREN) 10  
Write Disable (WRDI)/ Exit  
secured OTP mode  
Enter secured OTP mode  
(ENSO)  
-
-
-
-
100MHz  
-
-
-
-
-
B1H Hi-Z  
ABH Hi-Z  
ABH Hi-Z  
ABH Hi-Z  
ABH Hi-Z  
-
-
-.  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Release from Deep Power  
Down (RDP)  
-
-
-
-
-
-
-
Read Electronic Signature  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15H  
35H  
75H  
(RES) 8  
RES in secured OTP mode  
& not lock down  
RES in secured OTP mode  
& lock down  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Mar. 2009  
Revision: 1.0 12/36  
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