ESMT
F25L08PA
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write-Enable-
Latch bit in the Software Status Register to 1 allowing Write
operations to occur.
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
The WREN instruction must be executed prior to any Write
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
06
MSB
HIGH IMPENANCE
SO
Figure 17: Write Enable (WREN) Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write-Enable-
Latch bit to 0 disabling any new Write operations from occurring
or exits from OTP mode to normal mode.
CE must be driven high before the WRDI instruction is
executed.
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
04
MSB
HIGH IMPENANCE
SO
Figure 18: Write Disable (WRDI) Sequence
Enable Write Status Register (EWSR)
The Enable Write Status Register (EWSR) instruction arms the
Write Status Register (WRSR) instruction and opens the status
register for alteration. The Enable Write Status Register
instruction does not have any effect and will be wasted, if it is not
followed immediately by the Write Status Register (WRSR)
instruction. CE must be driven low before the EWSR instruction
is entered and must be driven high before the EWSR instruction
is executed.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.7
17/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
