ESMT
F25L04UA
TABLE 10: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Typical Specification
Units
Cycles
Years
mA
Test Method
1
NEND
100,000
10
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
Data Retention
Latch Up
1
ILTH
100 + IDD
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11 : AC OPERATING CHARACTERISTICS
Normal 33MHz Fast 50 MHz Fast 75 MHz Fast 100 MHz
Symbol
Parameter
Units
Min
Max
Min
Max
Min
Max
Min
Max
FCLK
TSCKH
TSCKL
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
33
50
75
100
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
13
5
9
9
6
6
5
5
1
TCES
5
5
5
CE Active Setup Time
CE Active Hold Time
CE Not Active Setup Time
CE Not Active Hold Time
CE High Time
1
TCEH
5
5
5
5
1
TCHS
5
5
5
5
1
TCHH
5
5
5
5
TCPH
100
100
100
100
TCHZ
9
9
9
9
CE High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
TCLZ
0
3
3
5
5
5
5
0
3
3
5
5
5
5
0
3
3
5
5
5
5
0
3
3
5
5
5
5
TDS
TDH
Data In Hold Time
THLS
HOLD Low Setup Time
HOLD High Setup Time
HOLD Low Hold Time
THHS
THLH
THHH
HOLD High Hold Time
THZ
9
9
9
9
9
9
9
9
HOLD Low to High-Z Output
HOLD High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
TLZ
TOH
0
0
0
0
TV
12
9
9
7
1. Relative to SCK.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 1.2 18/25
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
