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F25L04UA-75PG 参数 Datasheet PDF下载

F25L04UA-75PG图片预览
型号: F25L04UA-75PG
PDF下载: 下载PDF文件 查看货源
内容描述: 3V只有4兆位串行闪存 [3V Only 4 Mbit Serial Flash Memory]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 25 页 / 271 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F25L04UA  
Auto Address Increment (AAI) Program  
The AAI program instruction allows multiple bytes of data to be  
programmed without re-issuing the next sequential address  
location. This feature decreases total programming time when  
the entire memory array is to be programmed. An AAI program  
instruction pointing to a protected memory area will be ignored.  
The selected address range must be in the erased state (FFH)  
when initiating an AAI program instruction.  
Prior to any write operation, the Write-Enable (WREN) instruction  
must be executed. The AAI program instruction is initiated by  
executing an 8-bit command, AFH, followed by address bits  
[A23-A0]. Following the addresses, the data is input sequentially  
BUSY bit in the software status register or wait TBP for the  
completion of each internal self-timed Byte-Program cycle. Once  
the device completes programming byte, the next sequential  
address may be program, enter the 8-bit command, AFH,  
followed by the data to be programmed. When the last desired  
byte had been programmed, execute the Write-Disable (WRDI)  
instruction, 04H, to terminate AAI. After execution of the WRDI  
command, the user must poll the Status register to ensure the  
device completes programming. See Figure  
programming sequence.  
7
for AAI  
There is no wrap mode during AAI programming; once the  
highest unprotected memory address is reached, the device will  
exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0).  
from MSB (bit 7) to LSB (bit 0). CE must be driven high before  
the AAI program instruction is executed. The user must poll the  
TBP  
TBP  
CE  
15 16  
31 32 333435 36 373839  
MODE3  
0
1
2
3
4
5
6
7
8
23 24  
0
1
2
3
4
5
6
7
8
9 10 11 1213 14 15  
Data Byte 2  
0 1  
SCK MODE0  
AF  
A[23,16]  
A[15,8]  
A[7,0]  
Da ta Byte 1  
AF  
SI  
TBP  
CE  
SCK  
SI  
0
1
2
3
4
5
6
7
8
9 101112 1314 15  
Last Data Byte  
0
1
2
3
4
5
6
7
8
9 10 11 1213 14 15  
0
1
2
3
4
5 6 7  
AF  
05  
04  
Read Status Register(RDSR)  
Instruction to verify end of  
AAI Operation  
Write Disable (WRDI)  
Instruction to terminate  
AAI Operation  
DOUT  
SO  
Figure 7 : AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2009  
Revision: 1.2 11/25