ESMT
SECTOR STRUCTURE
F25L04UA
Table1 : F25L04UA Sector Address Table
Symbol
11
10
9
8
7
6
5
4
3
2
1
0
Sector Size
(Kbytes)
8KB
4KB
4KB
16KB
32KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
Address range
7E000H – 7FFFFH
7D000H – 7DFFFH
7C000H – 7CFFFH
78000H – 7BFFFH
70000H – 77FFFH
60000H – 6FFFFH
50000H – 5FFFFH
40000H – 4FFFFH
30000H – 3FFFFH
20000H – 2FFFFH
10000H – 1FFFFH
00000H – 0FFFFH
Sector Address
A18
1
1
1
1
1
1
1
1
0
0
0
0
A17
1
1
1
1
1
1
0
0
1
1
0
0
A16
1
1
1
1
1
0
1
0
1
0
1
0
A15
1
1
1
1
0
X
X
X
X
X
X
X
A14
1
1
1
0
X
X
X
X
X
X
X
X
A13
1
0
0
X
X
X
X
X
X
X
X
X
A12
X
1
0
X
X
X
X
X
X
X
X
X
Table2 : F25L04UA Block Protection Table
Protection Level
0
1(1/8 memory array)
2(1/4 memory array)
3(all memory array)
BP1
0
0
1
1
BP0
0
1
0
1
Protected Memory Area
None
70000H –7FFFFH
60000H –7FFFFH
00000H –7FFFFH
Block Protection (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
BP1 and BP0 bits as long as
WP
is high or the
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are both 0. After power-up, BP1
and BP0 are set to1.
Block Protection Lock-Down (BPL)
WP
pin driven low (V
IL
), enables the Block-Protection
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP1, and BP0 bits. When the
WP
pin is driven high (V
IH
), the BPL bit has no effect and its value is
“Don’t Care”. After power-up, the BPL bit is reset to 0.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision:
1.2
3/25
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
