ESMT
F25L04UA
TABLE 10: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Typical Specification
Units
Cycles
Years
mA
Test Method
1
NEND
Endurance
100,000
10
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
Data Retention
Latch Up
1
ILTH
100 + IDD
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11 : AC OPERATING CHARACTERISTICS TA=0~70oC
Normal 33MHz Fast 50 MHz Fast 75 MHz Fast 100 MHz
VDD=2.7~3.6V VDD=2.7~3.6V VDD=2.7~3.6V VDD=3.2~3.6V
Symbol
FCLK
TSCKH
TSCKL
Parameter
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
Min
Max
Min
Max
Min
Max
Min
Max
Units
MHz
ns
33
50
75
100
13
13
5
9
9
6
6
5
5
ns
1
TCES
5
5
5
ns
CE Active Setup Time
CE Active Hold Time
CE Not Active Setup Time
CE Not Active Hold Time
CE High Time
1
TCEH
5
5
5
5
ns
1
TCHS
5
5
5
5
ns
1
TCHH
5
5
5
5
ns
TCPH
100
100
100
100
ns
TCHZ
9
9
9
9
ns
CE High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
TCLZ
0
3
3
5
5
5
5
0
3
3
5
5
5
5
0
3
3
5
5
5
5
0
3
3
5
5
5
5
ns
TDS
ns
TDH
Data In Hold Time
ns
THLS
ns
HOLD Low Setup Time
HOLD High Setup Time
HOLD Low Hold Time
THHS
ns
THLH
ns
THHH
ns
HOLD High Hold Time
THZ
9
9
9
9
9
9
9
9
ns
HOLD Low to High-Z Output
HOLD High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
TLZ
ns
TOH
0
0
0
0
ns
TV
12
9
9
7
ns
1. Relative to SCK.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 18/24
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
