ESMT
F25L04UA
Write-Status-Register (WRSR)
The Write-Status-Register instruction works in conjunction with
the Enable-Write-Status-Register (EWSR) instruction to write
new values to the BP1, BP0, and BPL bits of the status register.
The Write-Status-Register instruction must be executed
immediately after the execution of the Enable-Write-Status
-Register instruction (very next instruction bus cycle). This
two-step instruction sequence of the EWSR instruction followed
by the WRSR instruction works like SDP (software data
protection) command structure which prevents any accidental
alteration of the status register values. The Write-Status-Register
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, and BP1 bits in the status register
can all be changed. As long as BPL bit is set to 0 or WP pin is
driven high (VIH) prior to the low-to-high transition of the CE pin
at the end of the WRSR instruction, the BP0, BP1, and BPL bit in
the status register can all be altered by the WRSR instruction. In
this case, a single WRSR instruction can set the BPL bit to “1” to
lock down the status register as well as altering the BP0 and BP1
bit at the same time. See Table 3 for a summary description of
instruction will be ignored when WP is low and BPL bit is set to
WP and BPL functions. CE must be driven low before the
command sequence of the WRSR instruction is entered and
driven high before the WRSR instruction is executed. See Figure
13 for EWSR and WRSR instruction sequences.
“1”. When the WP is low, the BPL bit can only be set from “0” to
“1” to lockdown the status register, but cannot be reset from “1” to
“0”.
CE
0 1 2 3 4 5 6 7 8 9 1011 12 13 1415
MODE3
0 1 2 3 4 5 6 7
SCK MODE0
STATUS
REGISTER IN
50
7 6 5 4 3 2 1
0
SI
01
MSB
MSB
HIGH IMPENANCE
SO
Figure 13 : ENABLE-WRITE-STATUS-REGISTER (EWSR) AMD WRITE-STATUS-REGISTER (WRSR) SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2006
Revision: 1.1 15/24
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
