EN29LV160A
COMMON FLASH INTERFACE (CFI)
The common flash interface (CFI) specification outlines device and host systems software
interrogation handshake, which allows specific vendor-specified software algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-
independent, and forward- and backward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array
data.
The system can read CFI information at the addresses given in Tables 5-8. In word mode, the upper
address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The
device enters the CFI query mode and the system can read CFI data at the addresses given in
Tables 5–8. The system must write the reset command to return the device to the autoselect mode.
Table 5. CFI Query Identification String
Adresses
Adresses
(Word Mode) (Byte Mode)
Data
Description
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
0051h
0052h Query Unique ASCII string “QRY”
0059h
0002h
Primary OEM Command Set
0000h
0040h
Address for Primary Extended Table
0000h
0000h
Alternate OEM Command set (00h = none exists)
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists
0000h
Table 6. System Interface String
Addresses
Addresses
(Word Mode) (Byte Mode)
Data
Description
1Bh
36h
0027h Vcc Min (write/erase)
D7-D4: volt, D3 –D0: 100 millivolt
0036h Vcc Max (write/erase)
D7-D4: volt, D3 –D0: 100 millivolt
1Ch
38h
1Dh
1Eh
1Fh
20h
3Ah
3Ch
3Eh
40h
0000h Vpp Min. voltage (00h = no Vpp pin present)
0000h Vpp Max. voltage (00h = no Vpp pin present)
0004h
0000h
Typical timeout per single byte/word write 2^N µs
Typical timeout for Min, size buffer write 2^N µs (00h = not
supported)
21h
22h
23h
24h
25h
26h
42h
44h
46h
48h
4Ah
4Ch
000Ah Typical timeout per individual block erase 2^N ms
0000h Typical timeout for full chip erase 2^N ms (00h = not supported)
0005h Max. timeout for byte/word write 2^N times typical
0000h Max. timeout for buffer write 2^N times typical
0004h Max. timeout per individual block erase 2^N times typical
0000h Max timeout for full chip erase 2^N times typical (00h = not
supported)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
11
Rev. I, Issue Date: 2008/07/17
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
