EN25P05-75VIP 参数 Datasheet PDF下载

EN25P05

Write Enable (WREN) (06h)

The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write

Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk

Erase (BE) and Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the

instruction code, and then driving Chip Select (CS#) High.

Figure 5. Write Enable Instruction Sequence Diagram

Write Disable (WRDI) (04h)

The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status

Register to a 0. The Write Disable instruction is entered by driving Chip Select (CS#) low, shifting

the instruction code “04h” into the DI pin and then driving Chip Select (CS#) high. Note that the WEL

bit is automatically reset after Power-up and upon completion of the Write Status Register, Page

Program, Sector Erase, and Bulk Erase instructions.

Figure 6. Write Disable Instruction Sequence Diagram

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

9

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

Rev. C, Issue Date: 2008/01/17