EN25P05
All attempts to access the memory array during a Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle
continues unaffected.
Table 4. Instruction Set
Instruction Name
Byte 1
Code
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Write Enable
Write Disable
06h
04h
continuous
(2)
Read Status
Register
Write Status
Register
(1)
05h
(S7-S0)
S7-S0
01h
03h
0Bh
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
dummy
D7-D0
(Next byte)
(D7-D0)
continuous
Read Data
(Next Byte)
continuous
Fast Read
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
Next byte
continuous
Page Program
Sector Erase
02h
D8h
C7h
B9h
Bulk Erase
Deep Power-down
(4)
Release from Deep
Power-down, and
read Device ID
Release from Deep
Power-down
Manufacturer/
Device ID
Read Identification
dummy
dummy
dummy
(ID7-ID0)
(M7-M0)
ABh
(5)
dummy
dummy
(ID7-ID0)
90h
9Fh
00h
(M7-M0)
(ID15-ID8)
(ID7-ID0)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from
the device on the DO pin.
2. The Status Register contents will repeat continuously until CS# terminate the instruction.
3. All sectors may use any address within the sector.
4. The Device ID will repeat continuously until CS# terminate the instruction.
5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h at Byte 4 starts DID and alternate with MID.
Table 5. Manufacturer and Device Identification
OP Code
ABh
(M7-M0)
(ID15-ID0)
(ID7-ID0)
05h
90h
1Ch
1Ch
05h
9Fh
2010h
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
8
Rev. C, Issue Date: 2008/01/17
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
