EN25P05-75VIP 参数 Datasheet PDF下载

EN25P05

All other instructions are ignored while the device is in the Deep Power-down mode. This can be

used as an extra software protection mechanism, when the device is not in active use, to protect the

device from inadvertent Write, Program or Erase instructions.

Status Register.

The Status Register contains a number of status and control bits that can be read

or set (as appropriate) by specific instructions.

WIP bit.

The WIP bit indicates whether the memory is busy with a Write Status Register, Program or

Erase cycle.

WEL bit.

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

BP1, BP0 bits.

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area

to be software protected against Program and Erase instructions.

SRP bit.

The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect

(WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device

to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register

(SRP, BP1, BP0) become read-only bits.

Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and

other adverse system conditions that may compromise data integrity. To address this concern the

EN25P05 provides the following data protection mechanisms:

Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent

changes while the power supply is outside the operating specification.

Program, Erase and Write Status Register instructions are checked that they consist of a

number of clock pulses that is a multiple of eight, before they are accepted for execution.

All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set

the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:

– Power-up

– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction

completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction

completion or Bulk Erase (BE) instruction completion or

The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This

is the Software Protected Mode (SPM).

The Write Protect (WP#) signal allows the Block Protect (BP1, BP0) bits and Status Register

Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).

In addition to the low power consumption feature, the Deep Power-down mode offers extra

software protection from inadvertent Write, Program and Erase instructions, as all instructions

are ignored except one particular instruction (the Release from Deep Power-down instruction).

Table 3. Protected Area Sizes Sector Organization

Memory Content

BP1

Bit

1

1

0

0

BP0

Bit

1

0

1

0

Protected Sectors

Addresses

Density(KB)

Portion

All ( Sector 0 to 1)

000000h-00FFFFh

64KB

All sectors

PP(page program), and SE(sector erase) is enabled without checking address.

All sectors are protected against BE(bulk erase).

None

None

None

None

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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©2004 Eon Silicon Solution, Inc., www.essi.com.tw

Rev. C, Issue Date: 2008/01/17