S1D15E06 Series
flicker.
6.3 Oscillator circuit
Furthermore, the display clock generates internal
common timing, liquid crystal alternating signal(FR),
field start signal (CA) and drive pattern signal (Fl and
F2).
The FR normally generates 2-frame alternating drive
system drive waveform to the liquid crystal drive
circuit. The n-line reverse alternating drive waveform
is generated for each 4 × (a+1) line by setting data on the
n-line reverse drive register. When there is a display
quality problem including crosstalk,the problem may
be solved using the n-line reverse alternating drive.
Execute liquid crystal display to determine the number
of lines “n” for alternation.
A display clock is generated by the CR oscillator. The
oscillator circuit is enabled only when M/S = HIGH and
CLS = HIGH. Oscillation starts after input of the built-
in oscillator circuit ON command input.
When CLS = LOW, oscillation stops, and display clock
is input from the CL pin.
6.4 Display timing generation circuit
Timing signals are generated from the display clock to
the line address circuit and display data latch circuit.
Synchronized with display clock, display data is latched
in display data latch circuit, and is output to the segment
drive output pin. Reading of the display data into the
LCD drive circuit is completely independent of access
from the MPU to the display data RAM. Accordingly,
asynchronous access to the display data RAM during
LCD display does not give any adverse effect; like as
When you want to use the S1D15E06 series in multi-
chip configuration, supply display timing signal (FR,
CA, F1, F2, CL, DOF) to the slave side from the master
side. Table 6.5 shows the statuses of FR, CA, F1, F2,
CL, DOF.
Table 6.5
Operating mode
CL
FR, CA, F1, F2, DOF
Master (M/S = HIGH) Built-in oscillator circuit enabled (CLS = HIGH) Output
Built-in oscillator circuit disabled (CLS = LOW) Input
Output
Output
Slave (M/S = LOW) Built-in oscillator circuit enabled (CLS = HIGH) Input
Built-in oscillator circuit disabled (CLS = LOW) Input
Input
Input
6.5 Liquid crystal drive circuit
6.5.1 SEG Drivers
This is a SEG output circuit. It selects the five values of
V2, V1, VC, MV1 and MV2 using the driver control
signal determined by the decoder, and output them.
6.5.2 COM Drivers
This is a COM output circuit. It selects three values of
V3, VC and MV3(VSS) using the driver control signal
determined by the decoder, and output them.
S1D15E06 series allows the COM output scanning
direction to be set by the common output status select
command. (See Table 6.6). This will reduce restrictions
on IC layout during LCD module assembling.
Table 6.6
Status
Direction of COM scanning
Normal
COM 0
→
→
COM 131
COM 0
Reverse COM 131
Rev. 2.1
EPSON
19
EPSON [ EPSON COMPANY ]
