Epson Research and Development
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Vancouver Design Center
3 S1D13506 Host Bus Interface
The S1D13506 implements a 16-bit Host Bus Interface specifically for interfacing to the
PR31500/PR31700 microprocessor.
The PR31500/PR31700 Host Bus Interface is selected by the S1D13506 on the rising edge
of RESET#. After releasing reset, the bus interface signals assume their selected
configuration. For details on S1D13506 configuration, see Section 4.2, “S1D13506 Config-
uration” on page 12.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 PR31500/PR31700 Host Bus Interface Pin Mapping
The following table shows the function of each Host Bus Interface signal.
Table 3-1: PR31500/PR31700 Host Bus Interface Pin Mapping
S1D13506 Pin Name
AB20
Philips PR31500/PR31700
ALE
AB19
/CARDREG
/CARDIORD
/CARDIOWR
VDD
AB18
AB17
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
WE1#
A[12:0]
D[23:16]
D[31:24]
/CARDxCSH
VDD
M/R#
CS#
VDD
BUSCLK
BS#
DCLKOUT
VDD
RD/WR#
RD#
/CARDxCSL
/RD
WE0#
/WE
WAIT#
RESET#
/CARDxWAIT
RESET#
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-009-02
EPSON [ EPSON COMPANY ]
