Epson Research and Development
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Vancouver Design Center
3 S1D13506 Host Bus Interface
The S1D13506 implements a 16-bit native PowerPC host bus interface which is used to
interface to the MPC821 microprocessor.
The PowerPC host bus interface is selected by the S1D13506 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13506 configuration, see Section 4.3, “S1D13506 Hardware Configu-
ration” on page 18.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 PowerPC Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal.
Table 3-1: PowerPC Host Bus Interface Pin Mapping
S1D13506 Pin Names
AB[20:0]
DB[15:0]
WE1#
PowerPC
A[11:31]
D[0:15]
BI
M/R#
External Decode
External Decode
CLKOUT
TS
CS#
BUSCLK
BS#
RD/WR#
RD#
RD/WR
TSIZ0
WE0#
TSIZ1
WAIT#
TA
RESET#
RESET#
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
EPSON [ EPSON COMPANY ]
