S1D13506 Register Summary
X25B-R-001-02
15 REG[02Ah], REG[02Bh] DRAM Timing Control Registers
21 REG[060h] CRT/TV Bit-per-pixel Select
Boolean Function for
Write Blit and Move
Blit
BitBlt ROP Code
Bits [3:0]
Boolean Function for Start Bit Positon for
Pattern Fill
Color Expansion
DRAM
MCLK Frequency
(MHz)
DRAM Timing
Control Reg 0
DRAM Timing
Control Reg 1
Bit-per-pixel Select Bits 1:0
Bit-per-pixel (bpp)
Reserved
4 bpp
DRAM Type
Speed (ns)
000-001
010
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
~D
~D
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
50
50
60
50
60
70
50
60
70
80
50
60
70
80
50
60
50
60
70
80
40
01h
01h
01h
12h
01h
00h
12h
12h
01h
00h
12h
12h
12h
01h
12h
01h
12h
12h
11h
01h
01h
01h
01h
02h
01h
00h
02h
02h
01h
01h
02h
02h
02h
01h
02h
01h
02h
02h
02h
01h
S ^ D
P ^ D
011
8 bpp
~S + ~D or ~(S . D)
~P + ~D or ~(P . D)
33
100
15 bpp
S . D
P . D
101
16 bpp
~(S ^ D)
D
~(P ^ D)
D
30
25
110-111
Reserved
~S + D
S
~P + D
P
EDO
22 REG[068h] CRT/TV Pixel Planning
S + ~D
S + D
P + ~D
P + D
Color Depth
4 bpp
Screen 2 Pixel Panning Bits Used
1 (Whiteness)
1 (Whiteness)
Bits [1:0]
Bit 0
8 bpp
20
25
20
15/16 bpp
---
29 REG[103h] BitBlt Operation Selection
BitBlt Operation Bits [3:0]
Blit Operation
Write Blit with ROP.
Read Blit.
23 REG[070h] LCD Ink/Cursor Selection
0000
0001
LCD Ink/Cursor Bits [1:0]
Mode
Inactive
Cursor
Ink
FPM
0010
Move Blit in positive direction with ROP.
Move Blit in negative direction with ROP.
Transparent Write Blit.
00
01
10
11
0011
0100
0101
Transparent Move Blit in positive direction.
Pattern Fill with ROP.
Reserved
0110
16 REG[030h] Panel Data Width
Panel Data Width Bits [1:0] Passive LCD Panel Data Width
0111
Pattern Fill with transparency.
Color Expansion.
24 REG[071h] LCD Ink/Cursor Start Address Encoding
1000
TFT/D-TFD Panel Data Width
1001
Color Expansion with transparency.
Move Blit with Color Expansion.
Move Blit with Color Expansion and transparency.
Solid Fill.
00
01
10
11
4-bit
8-bit
9-bit
12-bit
LCD Ink/Cursor Start Address Bits [7:0]
Start Address
Memory Size - 1024
Memory Size - n * 8192
1010
0
1011
16-bit
18-bit (64K color)
Reserved
n = 255...1
1100
Reserved
Other combinations
Reserved
25 REG[080h] CRT/TV Ink/Cursor Selection
17 REG[036h] LCD FPLINE Polarity Select
30 REG[104h],[105h],[106h] BitBlt Source Start Address Selection
CRT/TV Ink/Cursor Bits [1:0]
Mode
Inactive
Cursor
Ink
LCD FPLINE Polarity Select
Passive LCD FPLINE Polarity
active high
TFT FPLINE Polarity
active low
00
01
10
11
Color
Pattern Line
0
1
Pattern Base Address[20:0]
Pixel Offset[3:0]
Format
Offset[2:0]
active low
active high
BitBlt Source Start
Address[20:6], 6’b0
BitBlt Source Start
Address[5:3]
1’b0, BitBlt Source Start
8 bpp
Reserved
Address[2:0]
BitBlt Source Start
Address[20:7], 7’b0
BitBlt Source Start
Address[6:4]
BitBlt Source Start
Address[3:0]
18 REG[03Ch] LCD FPFRAME Polarity Select
16 bpp
26 REG[081h] CRT/TV Ink/Cursor Start Address Encoding
LCD FPFRAME Polarity Select Passive LCD FPFRAME Polarity
TFT FPFRAME Polarity
active low
31 REG[1E0h] LUT Mode Selection
0
1
active high
active low
CRT/TV Ink/Cursor Start Address Bits [7:0]
Start Address
Memory Size - 1024
Memory Size - n * 8192
active high
0
LUT Mode Bits [1:0]
Read
Write
n = 255...1
00
01
10
11
LCD LUT
LCD LUT
LCD and CRT/TV LUT’s
19 REG[040h] LCD Bit-per-pixel Select
LCD LUT
CRT/TV LUT
Reserved
CRT/TV LUT
Reserved
27 REG[100h] BitBlt Active Status
Bit-per-pixel Select Bits [1:0]
Color Depth (bpp)
000-001
010
Reserved
4 bpp
BitBlt Active Status
State
Write
Read
32 REG[1FCh] Display Mode Select
011
8 bpp
0
0
1
1
0
1
0
1
Idle
100
15 bpp
16 bpp
Reserved
Reserved
Display Mode Select Bits [2:0]
Display Mode Enabled
101
Initiatiating operation
Operation in progress
000
001
010
011
100
101
110
111
no display
LCD only
110-111
CRT only
20 REG[048h] LCD Pixel Planning
Double CRT and LCD
TV with flicker filter off
28 REG[102h] BitBlt ROP Code/Color Expansion Function Selection
Boolean Function for
Color Depth
4 bpp
Screen 2 Pixel Panning Bits Used
Double Display TV with flicker filter off and LCD
TV with flicker filter on
BitBlt ROP Code
Bits [3:0]
Boolean Function for Start Bit Positon for
Write Blit and Move
Blit
Bits [1:0]
Bit 0
Pattern Fill
Color Expansion
8 bpp
Double Display TV with flicker filter on and LCD
0000
0001
0010
0011
0100
0 (Blackness)
~S . ~D or ~(S + D)
~S . D
0 (Blackness)
~P . ~D or ~(P + D)
~P . D
bit 0
bit 1
bit 2
bit 3
bit 4
15/16 bpp
---
~S
~P
S . ~D
P . ~D
Page 4
01/02/08
EPSON [ EPSON COMPANY ]
