S1D13506 Register Summary
X25B-R-001-02
2
REG[032h] LCD HORIZONTAL DISPLAY WIDTH REGISTER
LCD Horizontal Display Width
Bit 4 Bit 3 Bit 2
RW
REG[04Ah] LCD DISPLAY FIFO HIGH THRESHOLD CONTROL REGISTER
LCD Display FIFO High Threshold
Bit 3 Bit 2
RW
REG[000h] REVISION CODE REGISTER
(For S1D13506: Product Code=000100b, Revision Code=01b)RO
Revision Code
Bit 1 Bit 0
Product Code
n/a
n/a
n/a
Bit 6
Bit 5
Bit 1
Bit 0
RW
Bit 5
Bit 4
Bit 1
Bit 1
Bit 1
Bit 0
RW
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[034h] LCD HORIZONTAL NON-DISPLAY PERIOD REGISTER
LCD Horizontal Non-Display Period
Bit 3 Bit 2 Bit 1
REG[04Bh] LCD DISPLAY FIFO LOW THRESHOLD CONTROL REGISTER
LCD Display FIFO Low Threshold
Bit 3 Bit 2
REG[001h] MISCELLANEOUS REGISTER
1/0
RW
n/a
n/a
n/a
n/a
n/a
Register/
Memory
Select
Reserved
Reserved
Reserved
Bit 4
Bit 0
RW
Bit 5
Bit 4
Bit 0
RW
n/a
n/a
n/a
n/a
REG[035h] TFT FPLINE START POSITION REGISTER
n/a n/a n/a
REG[050h] CRT/TV HORIZONTAL DISPLAY WIDTH REGISTER
CRT/TV Horizontal Display Width
Bit 4 Bit 3 Bit 2
3
REG[004h] GENERAL I/O PINS CONFIGURATION REGISTER
1/0
RW
TFT FPLINE Start Position
n/a
GPIO3 Pin GPIO2 Pin GPIO1 Pin
I/O Config I/O Config I/O Config
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
Bit 6
Bit 5
Bit 0
RW
Reserved
Reserved
Reserved
Reserved
Reserved
17
REG[036h] TFT FPLINE PULSE WIDTH REGISTER
REG[052h] CRT/TV HORIZONTAL NON-DISPLAY PERIOD REGISTER
CRT/TV Horizontal Non-Display Period
Bit 4 Bit 3 Bit 2
REG[008h] GENERAL I/O PINS CONTROL REGISTER
Reserved Reserved Reserved Reserved
RW
LCD
TFT FPLINE Pulse Width
GPIO3 Pin GPIO2 Pin GPIO1 Pin
n/a
n/a
FPLINE
n/a
n/a
n/a
Reserved
Bit 5
Bit 1
Bit 1
Bit 0
RW
I/O Status
I/O Status
I/O Status
Bit 3
Bit 2
Bit 1
Bit 1
Bit 0
Polarity Slct
REG[053h] CRT/TV HRTC START POSITION REGISTER
CRT/TV HRTC Start Position
REG[00Ch] MD CONFIGURATION READBACK REGISTER 0
RW
REG[038h] LCD VERTICAL DISPLAY HEIGHT REGISTER 0
LCD Vertical Display Height
RW
MD[7]
Status
MD[6]
Status
MD[5]
Status
MD[4]
Status
MD[3]
Status
MD[2]
Status
MD[1]
Status
MD[0]
Status
n/a
n/a
Bit 5
Bit 4
Bit 3
Bit 2
Bit 0
RW
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
n/a
Bit 0
RW
REG[00Dh] MD CONFIGURATION READBACK REGISTER 1
RW
REG[054h] CRT HRTC PULSE WIDTH REGISTER
REG[039h] LCD VERTICAL DISPLAY HEIGHT REGISTER 1
n/a n/a n/a n/a
MD[15]
Status
MD[14]
Status
MD[13]
Status
MD[12]
Status
MD[11]
Status
MD[10]
Status
MD[9]
Status
MD[8]
Status
CRT HRTC Pulse Width
CRT HRTC
Polarity Slct
LCD Vertical Display
Height
n/a
n/a
n/a
Bit 3
Bit 2
Bit 1
Bit 0
RW
n/a
Bit 9
Bit 1
Bit 1
Bit 8
4
REG[010h] MEMORY CLOCK CONFIGURATION REGISTER
RW
REG[056h] CRT/TV VERTICAL DISPLAY HEIGHT REGISTER 0
CRT/TV Vertical Display Height
Bit 4 Bit 3
MCLK
MCLK
n/a
n/a
n/a
n/a
n/a
n/a
n/a
REG[03Ah] LCD VERTICAL NON-DISPLAY PERIOD REGISTER
RW
Divide Slct
Source Slct
LCD Vertical Non-Display Period
Bit 3 Bit 2
Bit 7
Bit 6
Bit 5
Bit 2
n/a
Bit 1
Bit 0
RW
LCD VNDP
Status(RO)
n/a
5,6
REG[014h] LCD PIXEL CLOCK CONFIGURATION REGISTER
RW
Bit 5
Bit 4
Bit 0
RW
LCD PCLK Divide Select
LCD PCLK Source Select
Bit 1 Bit 0
REG[057h] CRT/TV VERTICAL DISPLAY HEIGHT REGISTER 1
n/a n/a n/a n/a n/a
n/a
n/a
n/a
REG[03Bh] TFT FPFRAME START POSITION REGISTER
TFT FPFRAME Start Position
Bit 1
Bit 0
CRT/TV Vertical Display
Height
n/a
n/a
7,8
Bit 9
Bit 1
Bit 1
Bit 8
REG[018h] CRT/TV PIXEL CLOCK CONFIGURATION REGISTER
RW
CRT/TV PCLK Source Slct
Bit 1 Bit 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 0
CRT/TV
PCLK 2X
Enable
CRT/TV PCLK Divide Slct
Bit 1 Bit 0
n/a
n/a
n/a
n/a
18
REG[058h] CRT/TV VERTICAL NON-DISPLAY PERIOD REGISTER
RW
REG[03Ch] TFT FPFRAME PULSE WIDTH REGISTER
RW
CRT/TV
VNDP
Status (RO)
CRT/TV Vertical Non-Display Period
Bit 4 Bit 3 Bit 2
LCD
TFT FPFRAME Pulse Width
FPFRAME
n/a
n/a
n/a
n/a
Bit 6
Bit 5
Bit 0
9,10
Bit 2
Bit 1
Bit 0
REG[01Ch] MEDIAPLUG CLOCK CONFIGURATION REGISTER
RW
Polarity Slct
MediaPlug Clock Divide
Select
MediaPlug Clock Source
Select
19
REG[059h] CRT/TV VRTC START POSITION REGISTER
CRT/TV VRTC Start Position
RW
n/a
n/a
n/a
REG[040h] LCD DISPLAY MODE REGISTER
RW
Bit 1
Bit 0
Bit 1
Bit 0
LCD Bit-per-pixel Select
LCD Display
Blank
SwivelView
Enable Bit 1
n/a
n/a
n/a
n/a
n/a
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 0
Bit 2
Bit 1
Bit 0
11
REG[01Eh] CPU TO MEMORY WAIT STATE SELECT REGISTER
RW
CPU to Memory Wait State
Select
REG[05Ah] CRT/TV VRTC PULSE WIDTH REGISTER
RW
REG[041h] LCD MISCELLANEOUS REGISTER
n/a n/a n/a
RW
n/a n/a n/a n/a n/a
n/a
n/a
CRT VRTC Pulse Width
CRT VRTC
Polarity Slct
Dual Panel
Buffer
Disable
n/a
n/a
n/a
n/a
Dithering
Disable
Bit 1
Bit 0
n/a
n/a
Bit 2
Bit 1
Bit 0
12
REG[020h] MEMORY CONFIGURATION REGISTER
n/a n/a n/a n/a
RW
REG[05Bh] CRT/TV OUTPUT CONTROL REGISTER
TV TV
RW
REG[042h] LCD DISPLAY START ADDRESS REGISTER 0
LCD Display Start Address
Bit 4 Bit 3
RW
Memory Type
Bit 1 Bit 0
TV S-Video/
Composite
Output Slct Output Slct
TV PAL/
NTSC
n/a
n/a
DAC Output
Level Select
n/a
n/a
Chrominance Luminance
Filter Enable Filter Enable
n/a
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
RW
13,14
REG[021h] DRAM REFRESH RATE REGISTER
RW
21
REG[060h] CRT/TV DISPLAY MODE REGISTER
RW
REG[043h] LCD DISPLAY START ADDRESS REGISTER 1
LCD Display Start Address
Refresh Select
n/a
DRAM Refresh Rate
Bit 1
n/a
CRT/TV
Display
Blank
CRT/TV Bit-per-pixel Select
Bit 1
Bit 0
Bit 2
Bit 0
RW
n/a
n/a
n/a
n/a
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 8
RW
15
REG[02Ah] DRAM TIMING CONTROL REGISTER 0
DRAM Timing Control
REG[044h] LCD DISPLAY START ADDRESS REGISTER 2
n/a n/a n/a n/a
REG[062h] CRT/TV DISPLAY START ADDRESS REGISTER 0
CRT/TV Display Start Address
Bit 4 Bit 3
RW
LCD Display Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
n/a
Bit 1
Bit 0
Bit 19
Bit 18
Bit 2
Bit 17
Bit 1
Bit 16
RW
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
RW
15
REG[02Bh] DRAM TIMING CONTROL REGISTER 1
n/a n/a n/a n/a
RW
DRAM Timing Control
Bit 9 Bit 8
REG[046h] LCD MEMORY ADDRESS OFFSET REGISTER 0
LCD Memory Address Offset
REG[063h] CRT/TV DISPLAY START ADDRESS REGISTER 1
CRT/TV Display Start Address
Bit 12 Bit 11
n/a
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 0
RW
Bit 15
Bit 14
Bit 13
Bit 10
Bit 8
RW
16
REG[030h] PANEL TYPE REGISTER
RW
REG[047h] LCD MEMORY ADDRESS OFFSET REGISTER 1
n/a n/a n/a n/a
REG[064h] CRT/TV DISPLAY START ADDRESS REGISTER 2
n/a n/a n/a n/a
EL Panel
Mode
Enable
Panel Data Width
Panel Data
Format
Select
Color/Mono Dual/Single TFT/Passive
Panel Select Panel Select Panel Select
n/a
LCD Memory Address Offset
Bit 10 Bit 9 Bit 8
CRT/TV Display Start Address
Bit 1
Bit 0
n/a
Bit 19
Bit 18
Bit 17
Bit 16
RW
REG[031h] MOD RATE REGISTER
RW
20
REG[048h] LCD PIXEL PANNING REGISTER
n/a n/a n/a
RW
LCD Pixel Panning
Bit 1 Bit 0
REG[066h] CRT/TV MEMORY ADDRESS OFFSET REGISTER 0
CRT/TV Memory Address Offset
Bit 4 Bit 3
MOD Rate
Bit 3 Bit 2
n/a
n/a
Bit 5
Bit 4
Bit 1
Bit 0
n/a
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
Page 1
01/02/08
EPSON [ EPSON COMPANY ]
