Epson Research and Development
Page 75
Vancouver Design Center
9. Program the Foreground Color Registers to the foreground color. REG[119h] is set to
00h and REG[118h] is set to 86h (134 decimal).
Note that for 15/16 bpp color depths REG[119h] and Reg[118h] are both required and
programmed directly with the value of the foreground color.
10. Program the BitBLT Color Format Register for 8 bpp operation. REG[101h] is set to
00h.
11. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
BltMemoryOffset = ScreenStride ÷ 2
= 640 ÷ 2
= 140h
REG[10Dh] is set to 01h and REG[10Ch] is set to 40h.
12. Calculate the number of WORDS the blit engine expects to receive.
First, the number of WORDS in one blit line must be calculated as follows.
nWordsOneLine
= ((125 MOD 16) + 12 + 15) ÷ 16
= (13 + 12 + 15) ÷ 16
= 40 ÷ 16
= 2
Therefore, the total WORDS the blit engine expects to receive is calculated as fol-
lows.
nWords
= nWordsOneLine × 18
= 2 × 18
= 36
13. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (Bit-
BLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation and wait for the Blit Engine to start. REG[100h] is set to 80h,
then wait until REG[100h] bit 7 returns a 1.
14. Prior to writing all nWORDS to the Blit FIFO, confirm the Blit FIFO is not full
(REG[100h] bit 4 returns a 0). One WORD expands into 16 pixels which fills all 16
FIFO words in 15/16 bpp or 8 FIFO words in 8 bpp.
The following table summarizes how many words can be written to the Blit FIFO.
Table 10-5: Possible Blit FIFO Writes
BitBLT Control Register 0 (REG[100h])
8 bpp Word
16 bpp Word
Writes Available
Writes Available
FIFO Not Empty Status
FIFO Half Full Status
FIFO Full Status
0
1
1
1
0
0
1
1
0
0
0
1
2
1
1
0 (do not write)
0 (do not write)
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
EPSON [ EPSON COMPANY ]
