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Epson Research and Development
Vancouver Design Center
2 Features
2.1 Memory Interface
• 16-bit DRAM interface:
• EDO-DRAM up to 40MHz data rate (80M Bytes/s).
• FPM-DRAM up to 25MHz data rate (50M Bytes/s).
• Memory size options:
• 512K bytes using one 256K×16 device.
• 2M bytes using one 1M×16 device.
• A configuration register can be programmed to enhance performance by tailoring the
memory control output timing to the DRAM device.
• The complete 2M byte display buffer address space is directly and contiguously avail-
able through the 21-bit address bus.
2.2 CPU Interface
• Supports the following interfaces:
• Epson E0C33 (16-bit interface to 32-bit microprocessor).
• Hitachi SH-4 bus interface.
• Hitachi SH-3 bus interface.
• MIPS/ISA.
• Motorola MC68000 (16-bit interface to 16/32-bit microprocessor/microcontroller).
• Motorola MC68030 (16-bit interface to 16/32-bit microprocessor/microcontroller).
• Motorola PowerPC MPC82x (16-bit interface to 32-bit microprocessor).
• MPU bus interface with programmable READY.
• NEC MIPS VR41xx.
• PC Card (PCMCIA).
• Philips MIPS PR31500/31700.
• Toshiba MIPS TX39xx.
• StrongARM (PC Card).
• One-stage write buffer for minimum wait-state CPU writes.
• Registers are memory-mapped – the M/R# pin selects between display buffer and
register address space.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
