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Epson Research and Development
Vancouver Design Center
19 Power Save Mode
The S1D13506 has been designed for very low-power applications. During normal
operation, internal clock networks are dynamically disabled when not required. Similarly,
the LCD and/or CRT/TV pipelines are shut down when not required in the selected display
mode. Additionally, the S1D13506 has a software initiated power save mode.
19.1 Display Modes
The S1D13506 resets with both displays inactive, i.e. neither the LCD nor CRT/TV
pipelines are active. The displays are independently enabled/disabled by REG[1FCh] bits
2-0: the CRT/TV is instantaneously enabled/disabled by these bits; the LCD is powered
up/down according to the sequences in Section 7.4, “Power Sequencing” on page 78.
19.2 Power Save Mode
Power save mode is invoked by setting REG[1F0h] bit 0 to 1. In power save mode, both
displays are disabled: the CRT/TV is instantaneously disabled; the LCD is powered down
according to the sequences in Section 7.4, “Power Sequencing” on page 78. Access to
memory is not allowed and the memory controller merely refreshes the memory in the
method selected by REG[021h]. Register access is allowed.
19.3 Power Save Status Bits
LCD Power Save Status bit
The LCD Power Save Status bit (REG[1F1h] bit 0), when 1, indicates that the panel is
powered down. When this bit is 0, the panel is powered up, or in transition of powering up
or down. The system may disable the LCD pixel clock source when this bit is 1. This bit is
1 after chip reset.
Memory Controller Power Save Status bit
The Memory Controller Power Save Status bit (REG[1F1h] bit 1, when 1, indicates that the
DRAM interface is powered down - the DRAM is either in self-refresh mode or completely
idle. This condition occurs shortly after power save mode is invoked, provided Self-Refresh
or No Refresh is pre-selected (see REG[021h] bits 7-6); this condition will never occur if
CBR Refresh is selected. When this bit is 0, the DRAM interface is active. The system may
disable the memory clock source when this bit is 1. This bit is 0 after chip reset.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
