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S1D13506 参数 Datasheet PDF下载

S1D13506图片预览
型号: S1D13506
PDF下载: 下载PDF文件 查看货源
内容描述: S1D13506彩色LCD / CRT / TV控制器 [S1D13506 Color LCD/CRT/TV Controller]
分类和应用: 电视控制器
文件页数/大小: 696 页 / 5934 K
品牌: EPSON [ EPSON COMPANY ]
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Epson Research and Development  
Page 179  
Vancouver Design Center  
Solid Fill  
The Solid Fill Blit fills a specified blit area with a solid color as defined in the Foreground  
Color Register. In 8 bpp mode, only the low byte of the Foreground Color is used for solid  
fill.  
Pattern Fill  
The Pattern Fill Blit fills a specified blit area with an 8 pixel by 8 line pattern in full color  
defined in off-screen display buffer. The pattern data has to be stored in a contiguous  
address (i.e. for 8 and 16 bpp, the pattern data will occupy 64 and 128 bytes respectively  
starting from the base address).  
Any pixel within the 8x8 pattern can be used to start the fill area. The least significant bits  
of the source address start register are used to specify the starting pixel.  
The 2D engine can detects the end of each line and continues from the beginning of the next  
line. When the last line of pattern is encountered, the first line of the pattern will be drawn  
on the following line.  
Supports two full 16-bit operand ROP functions.  
Note  
The BitBlt operation Pattern Fill with ROP requires a BitBlt width ≥ 2. The BitBlt width  
is set in REG[110h], REG[111h].  
Transparent Pattern Fill  
The Transparent Pattern Fill fills a specified blit area with an 8 pixel by 8 line pattern in full  
color defined in off-screen display buffer. The pattern data has to be stored in a contiguous  
address (i.e. for 8 and 16 bpp, the pattern data will occupy 64 and 128 bytes respectively  
starting from the base address).  
When the pattern color is equal to the key color, which is defined in Background Color  
Register, the destination area is not updated. In 8 bpp mode, only the low byte of the key  
color is used for comparison.  
For this blit no raster operation is applied.  
Note  
The BitBlt operation Pattern Fill with transparency requires a BitBlt width ≥ 2. The  
BitBlt width is set in REG[110h], REG[111h].  
Transparent Write Blit  
The Transparent Write Blit supports bit block transfers from the host to display buffer.  
Hardware Functional Specification  
Issue Date: 01/02/06  
S1D13506  
X25B-A-001-10  
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