Epson Research and Development
Page 99
Vancouver Design Center
7.5.7 Single Color 16-Bit Panel Timing with External Circuit
VNDP
VDP
FPFRAME
FPLINE
DRDY (MOD)
LINE 1
LINE 2
LINE 3
LINE 4
LINE 479
LINE 480
LINE 1
LINE 2
FPDAT[15:0]
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
1-G1
1-R2
1-R1
1-R636
1-B635
1-G636 1-B636
1-G637
1-R637
FPDAT7
FPDAT6
FPDAT5
FPDAT4
1-B1
1-G2
1-R3
1-B3
1-G4
1-R5
1-B5
1-B2
1-G3
1-R4
1-B4
1-B637 1-R638
1-G638 1-B638
1-R639 1-G639
1-B 639 1-R640
FPDAT3
FPDAT2
1-G5
1-R6
FPDAT1
FPDAT0
1-G640
1-B640
1-R1
1-B1
1-G2
1-R3
1-B3
1-G4
1-R5
1-B5
1-G635
1-G636
1-R637
1-B637
1-G638
D15
D14
D13
D12
D11
D10
D9
1-R639
1-B 639
1-G640
D8
1-G1
1-R2
1-B2
1-G3
1-R636
1-B636
1-G637
1-R638
D7
D6
D5
D4
1-B638
1-G639
1-R640
1-B640
1-R4
1-B4
1-G5
1-R6
D3
D2
D1
D0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-34: 16-Bit Single Color Panel Timing with External Circuit
VDP
VNDP
HDP
= Vertical Display Period
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
HNDP
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
