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EM47FM3288SBB 参数 Datasheet PDF下载

EM47FM3288SBB图片预览
型号: EM47FM3288SBB
PDF下载: 下载PDF文件 查看货源
内容描述: 16GB ( 64mA的?? 8Bankà ?? 32 ),双数据速率3 SDRAM堆叠 [16Gb (64M×8Bank×32) Double DATA RATE 3 Stack SDRAM]
分类和应用: 动态存储器
文件页数/大小: 41 页 / 1147 K
品牌: EOREX [ EOREX CORPORATION ]
 浏览型号EM47FM3288SBB的Datasheet PDF文件第19页浏览型号EM47FM3288SBB的Datasheet PDF文件第20页浏览型号EM47FM3288SBB的Datasheet PDF文件第21页浏览型号EM47FM3288SBB的Datasheet PDF文件第22页浏览型号EM47FM3288SBB的Datasheet PDF文件第24页浏览型号EM47FM3288SBB的Datasheet PDF文件第25页浏览型号EM47FM3288SBB的Datasheet PDF文件第26页浏览型号EM47FM3288SBB的Datasheet PDF文件第27页  
EM47FM3288SBB  
AC Operating Test Characteristics  
(VDD, VDDQ=1.5V±0.075V)  
Speed Bin  
-125 (DDR3-1600)  
-150 (DDR3-1333)  
Symbol  
CL-nRCD-nRP  
Parameter  
11-11-11  
9-9-9  
Units Notes  
Min.  
Max.  
Min.  
195  
Max.  
-
Write leveling setup time from  
rising CK,/CK crossing to rising  
DQS,/DQS crossing  
tWLS  
165  
-
ps  
ps  
Write leveling hold time from  
rising DQS,/DQS crossing to  
rising CK,/CK crossing  
tWLH  
165  
-
195  
-
tWLO  
tWLOE  
Write leveling output delay  
Write leveling output error  
Absolute clock period  
0
0
7.5  
2
CK (avg)max+  
tJIT (per)max  
0
0
9
2
ns  
ns  
ps  
tCK (avg)min+  
tJIT(per)min  
t
t
CK (avg)min+  
tJIT (per)min  
t
CK (avg)max+  
tJIT (per)max  
tCK (abs)  
tCK  
(avg)  
tCH (abs)  
Absolute clock high pulse width  
0.43  
-
0.43  
-
30  
31  
tCK  
(avg)  
tCL (abs)  
tJIT (per)  
Absolute clock low pulse width  
Clock period jitter  
0.43  
-70  
-60  
-
-
0.43  
-80  
-70  
-
-
70  
80  
ps  
ps  
ps  
ps  
Clock period jitter during DLL  
locking period  
tJIT (per,lck)  
tJIT (cc)  
60  
70  
Cycle to cycle period jitter  
140  
120  
160  
140  
Cycle to cycle period jitter during  
DLL locking period  
tJIT (cc,lck)  
-
-
tERR (2per)  
tERR (3per)  
tERR (4per)  
tERR (5per)  
tERR (6per)  
tERR (7per)  
tERR (8per)  
tERR (9per)  
Cumulative error across 2 cycles  
Cumulative error across 3 cycles  
Cumulative error across 4 cycles  
Cumulative error across 5 cycles  
Cumulative error across 6 cycles  
Cumulative error across 7 cycles  
Cumulative error across 8 cycles  
Cumulative error across 9 cycles  
-103  
-122  
-136  
-147  
-155  
-163  
-169  
-175  
103  
122  
136  
147  
155  
163  
169  
175  
-118  
-140  
-155  
-168  
-177  
-186  
-193  
-200  
118  
140  
155  
168  
177  
186  
193  
200  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
Cumulative error across 10  
cycles  
tERR (10per)  
tERR (11per)  
tERR (12per)  
-180  
-184  
-188  
180  
184  
188  
-205  
-210  
-215  
205  
210  
215  
ps  
ps  
ps  
Cumulative error across 11  
cycles  
Cumulative error across 12  
cycles  
Cumulative error across  
n= 13,14,… 49,50 cycles  
tERR (nper)min=(1+0.68ln(n))*tJIT (per)min  
ERR (nper)max=(1+0.68ln(n))*tJIT (per)max  
tERR (nper)  
ps  
32  
t
Jul. 2012  
23/41  
www.eorex.com  
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