EM47CM1688SBB
Differential swing requirements for clock (CK - /CK) and strobe (DQS - /DQS)
- Allowed time before ringback (tDVAC) for CK - /CK and DQS - /DQS
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(ac)| = 350mV
tDVAC [ps] @ |VIH/Ldiff(ac)| = 300mV
-
Min
75
57
50
38
34
29
22
13
0
Max
Min
175
170
167
163
162
161
159
155
150
150
Max
>4.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
<1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, /CK, /DQS) has also to comply with certain
requirements for single-ended signals.
CK and /CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels
(VIH(AC) / VIL(AC) ) for Address/Command signals) in every half-cycle.
DQS, /DQS have to reach VSEHmin / VSELmax [approximately the ac-levels (VIH(AC) / VIL(AC) ) for DQ
signals] in every half-cycle preceding and following a valid transition.
Note that the applicable AC-levels for Address/Command and DQ’s might be different per speed-bin etc. E.g., if
VIHCA(AC150)/VILCA(AC150) is used for Address/Command signals, then these AC-levels apply also for the
single-ended components of differential CK and /CK.
Jun. 2012
10/38
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