EM47CM1688SBB
Pin Description (Continued)
DQSU,
C7,B7,F3,G3
DQSU
,
(Data Strobe)
Output with read data, input with write data. Edge-aligned with read data,
centered in write data. DQSL corresponds to the data on DQL0-DQL7;
DQSU corresponds to the data on DQU0-DQU7. The data strobes DQSL,
DQSL,
DQSL
J3, K3, L3
RAS
,
CAS
,
WE
and DQSU are paired with differential signals
DQSU
and
DQSL
respectively, to provide differential pair signaling to the system during
reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
(Command Inputs)
RAS
,
CAS
&
WE
(along with
CS
) define the command being entered.
(Input Data Mask)
D3,E7
DMU,DML
DMU & DML are input mask signal for write data. Input data is masked
when DMU or DML are sampled HIGH coincident with that input data
during a write access. DMU & DML is sampled on both edges of DQSU &
DQML respectively.
(Data Input/Output)
D7,C3,C8,C2,A7,
A2,B8,A3
E3,F7,F2,F8,H3,
H8,G2,H7
B2,D9,G7,K2,K9,N
1,N9,R1,R9/A9,B3,
E1,G8,J2,J8,M1,M
9,P1,P9,T1,T9
A1,A8,C1,C9,D2,E
9,F1,H2,H9 /B1,
B9,D1,D8,E2,E8,
F9,G1,G9
L8
DQU0~7
DQL0~7
Data inputs and outputs are on the same pin.
(Data Input/Output)
Data inputs and outputs are on the same pin.
(Power Supply/Ground)
VDD/VSS
VDD and VSS are power supply for internal circuits.
(DQ Power Supply/DQ Ground)
VDDQ,
/VSSQ
ZQ
VDDQ and VSSQ are power supply for the output buffers.
(ZQ Calibration)
Reference pin for ZQ calibration
(Active Low Asynchronous Reset)
T2
Reset is active when
RESET
is LOW, and inactive when
RESET
is
RESET
HIGH.
RESET
must be HIGH during normal operation.
RESET
is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e.
1.20V for DC high and 0.30V for DC low.
(Reference Voltage)
H1
M8
J1,J9,L1,L9,
M7,T3, T7
VREFDQ
VREFCA
NC
Reference voltage for DQ
(Reference Voltage)
Reference voltage for CA
(No Connection)
No internal electrical connection is present.
Note: Input pins only BA0-BA2, A0-A12,
RAS
,
CAS
, WE ,
CS
, CKE, ODT and
RESET
do not supply
termination.
Jun. 2012
6/38
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