EN29LV641H/L EN29LV640U
Any commands written to the device during the program operation are ignored. Programming status
can be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the
program operation is successfully completed, the device returns to read mode and the user can read
the data programmed to the device at that address. Note that data can not be programmed from a
“0” to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was successful. However, a succeeding read will show
that the data is still “0”. Only erase operations can convert a “0” to a “1”. When programming time
limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to
Read mode.
Programming is allowed in any sequence across sector boundaries.
Unlock Bypass
To speed up programming operation, the Unlock Bypass Command may be used. Once this feature
is activated, the shorter two-cycle Unlock Bypass Program command can be used instead of the
normal four-cycle Program Command to program the device. During the unlock bypass mode, only
the Unlock Bypass Program and Unlock Bypass Reset command can be accepted. This mode is
exited after issuing the Unlock Bypass Reset Command. The device powers up with this feature
disabled
The device provides accelerated program operations through the ACC pin. When ACC is asserted
to VHH, the device automatically enters the Unlock Bypass mode. The system may then write the
two-cycle Unlock Bypass Program command sequence.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these
operations. The Command Definitions table shows the address and data requirements for the chip
erase command sequence.
Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and addresses are no longer latched.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by
writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are
then followed by the address of the sector to be erased, and the sector erase command. The
Command Definitions table shows the address and data requirements for the sector erase
command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. If there are several sectors to be erased, Sector Erase Command
sequences must be issued for each sector. That is, only a sector address can be specified for
each Sector Erase command. Users must issue another Sector Erase command for the next
sector to be erased after the previous one is completed.
When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2005 Eon Silicon Solution, Inc., www.essi.com.tw
19
Rev. B, Issue Date: 2005/06/27
EON [ EON SILICON SOLUTION INC. ]
