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EN29LV400AB-70TI 参数 Datasheet PDF下载

EN29LV400AB-70TI图片预览
型号: EN29LV400AB-70TI
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512K ×8位/ 256K ×16位)闪存引导扇区快闪记忆体, CMOS 3.0伏只 [4 Megabit (512K X 8-bit / 256K X 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 41 页 / 378 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN29LV400A  
Unlock Bypass  
To speed up programming operation, the Unlock Bypass Command may be used. Once this feature  
is activated, the shorter two cycle Unlock Bypass Program command can be used instead of the  
normal four cycle Program Command to program the device. This mode is exited after issuing the  
Unlock Bypass Reset Command. The device powers up with this feature disabled.  
Chip Erase Command  
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing  
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then  
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The  
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm  
automatically preprograms and verifies the entire memory for an all zero data pattern prior to  
electrical erase. The system is not required to provide any controls or timings during these  
operations. The Command Definitions table shows the address and data requirements for the chip  
erase command sequence.  
Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.  
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write  
Operation Status” for information on these status bits. When the Embedded Erase algorithm is  
complete, the device returns to reading array data and addresses are no longer latched.  
Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations  
tables in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for  
timing waveforms.  
Sector Erase Command Sequence  
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by  
writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are  
then followed by the address of the sector to be erased, and the sector erase command. The  
Command Definitions table shows the address and data requirements for the sector erase  
command sequence.  
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other  
commands are ignored.  
When the Embedded Erase algorithm is complete, the device returns to reading array data and  
addresses are no longer latched. The system can determine the status of the erase operation by  
using DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits.  
Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations  
tables in the “AC Characteristics” section for parameters, and to the Sector Erase Operations Timing  
diagram for timing waveforms.  
Erase Suspend / Resume Command  
The Erase Suspend command allows the system to interrupt a sector erase operation and then read  
data from, or program data to, any sector not selected for erasure. This command is valid only  
during the sector erase operation. The Erase Suspend command is ignored if written during the chip  
erase operation or Embedded Program algorithm. Addresses are don’t-cares when writing the  
Erase Suspend command.  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2005 Eon Silicon Solution, Inc., www.essi.com.tw  
13  
Rev. A, Issue Date: 2005/01/07  
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