EN29LV320A
AC CHARACTERISTICS
Table 12. Read-only Operations Characteristics
Parameter
Speed Options
Symbols
Test
Description
Setup
JEDEC
Standard
-70
-90
Unit
Min
70
90
ns
tAVAV
tRC
Read Cycle Time
CE# = VIL
OE# = VIL
Max
Max
Max
Max
Max
70
70
30
20
20
90
90
35
20
20
ns
ns
ns
ns
ns
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tACC
tCE
tOE
tDF
Address to Output Delay
Chip Enable To Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z
Output Enable to Output High Z
OE# = VIL
tDF
Output Hold Time from
Addresses, CE# or OE#,
whichever occurs first
Min
0
0
ns
tAXQX
tOH
Read
Min
Min
0
0
ns
ns
Output Enable
Hold Time
tOEH
Toggle and
Data# Polling
10
10
Notes:
For - 70
Vcc = 3.0V – 3.6V
Output Load: 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Pulse Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
- 90
Vcc = 2.7V – 3.6V
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 5 ns
Input Pulse Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
Figure 3. AC Waveforms for READ Operations
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
36
Rev. B, Issue Date: 2007/07/17
EON [ EON SILICON SOLUTION INC. ]
