EN29F010
DATA PROTECTION
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with
W E
= V ,
= VIL and
= VIH, the device will not accept commands on the rising edge of
OE
CE
.
WE
IL
Low VCC Write Inhibit
During VCC power-up or power-down, the EN29F010 locks out write cycles to protect against any
unintentional writes. If VCC < VLOK, the command register is disabled and all internal program or
erase circuits are disabled. Under this condition, the device will reset to the READ mode.
Subsequent writes will be ignored until VCC > VLKO.
Write “Noise” Pulse Protection
Noise pulses less than 5ns on
command register.
,
or
will neither initiate a write cycle nor change the
WE
OE CE
Logical Inhibit
If
=V or
=V , writing is inhibited. To initiate a write cycle,
and
must be a logical
W E
CE
WE
,
CE
are all logical zero (not recommended usage), it will be considered a
IH
IH
“zero”. If
, and
CE
OE
W E
write.
Sector Protect and Unprotect
The hardware sector protection feature disables both program and erase operations in any sector.
The hardware sector unprotection feature re-enables both program and erase operation in
previously protected sectors.
Sector protection/unprotection must be implemented using programming equipment. The procedure
requires a high voltage (VID) on address pin A9 and the control pins. Contact Eon Silicon Solution,
Inc. for an additional supplement on this feature.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
14
Rev. A, Issue Date: 2003/10/20
EON [ EON SILICON SOLUTION INC. ]
